1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can reduce the frequency of a CBR (column before row) refresh operation.
2. Description of the Related Art
The storage capacity of a DRAM (dynamic random access memory) has been increased year by year, and in its progress, a DRAM having the capacity of one Gigabit has been manufactured on a trial basis. On the other hand, a technology for reducing a leak current of memory cells in a DRAM has been remarkably advanced with efforts to improve the semiconductor device fabrication process. Actually, however, the technology for reducing a leak current depends largely on the level of manufacturing technologies.
Specifically describing in terms of a holding time which refers to a time for which a memory cell can hold data therein without refresh operation, a first DRAM has a holding time of merely 200 milliseconds, whereas a second DRAM, which is identical in specifications to the first DRAM, can have a holding time of 800 milliseconds.
However, the specifications related to the holding time of DRAM define 64 milliseconds which can be achieved by any product. Therefore, in a device which is provided with DRAMs, CBR refresh commands are issued frequently enough to cover the address space of each DRAM during a period of 64 milliseconds. In this event, although the second DRAM has a holding time four times as long as the first DRAM, the second DRAM consumes a current associated with the CBR refresh operation equivalent to the first DRAM which has a shorter holding time.
In relation to the foregoing description, a dynamic semiconductor memory device is described in JP-A-7-93971. The semiconductor memory device disclosed in JP-A-7-93371 comprises a refresh address generator circuit for generating refresh addresses at a constant period, and a storage unit for storing refresh addresses which are classified into two or more types based on a set of bits indicative of the shortest pause time in the refresh addresses. This semiconductor memory device omits refresh operations in unnecessary cycles for those refresh addresses which belong to a class of refresh addresses that have pause times twice or more longer than the refresh address having the shortest pause time. In this way, unnecessary refresh operations at shorter periods are omitted for each address to reduce the power which would be otherwise consumed by the refresh operations.
In a semiconductor device disclosed in JP-A-11-39862, a row is selected at a period shorter than a period at which an external signal change. The semiconductor device has a test oscillator circuit which oscillates at a period shorter than a refresh oscillator circuit, which specifies the period of self-refresh operation, to generate an internal row address strobe signal. Upon selection of a special operation mode, the test oscillator circuit is activated by an external row address strobe signal (/RAS) to provide a row control circuit with the internal row address strobe signal through a selector. In this way, the internal row address strobe signal is generated at a period shorter than the period of the row address strobe signal /RAS to select a row.
In a semiconductor memory device disclosed in JP-A-11-120772, a bias voltage generator has a self-refresh function which automatically refreshes data in memory cells. The bias voltage generator is intermittently activated by an activation signal only when the refresh function is active. After activated by the activation signal, a self-refresh operation is periodically performed twice or more. In this way, a bias circuit intermittently operates in a self-refresh mode to reduce the proportion of a waiting time and additionally realize a reduction in a current consumed thereby.
A self-refresh circuit disclosed in JP-P2000-315385A comprises a binary counter circuit, a selector circuit, and a set/reset signal generator circuit. The selector circuit receives an external address signal and an output signal of the binary counter circuit, and delivers the external address signal as an internal address signal during a read/write cycle period. The selector circuit in turn delivers the output signal of the binary counter circuit as an internal address signal during a self-refresh period. The set/reset signal generator circuit generates a set/reset signal based on the external address signal. The binary counter circuit delivers an output signal which sequentially indicates addresses continuous to an address indicated by the external address signal, based on the set/reset signal, during the self-refresh period.
A self-refresh control circuit disclosed in JP-P2001-6356A can eliminate an intensive refresh operation for all words after a self-refresh operation to reduce excessive current consumption. A timer circuit indicates a predetermined operation timing. An internal binary counter operates at a timing indicated by the timer circuit to determine a row address for use in the self-refresh operation. A counter comparator compares the value on the internal binary counter at the start of a self-refresh operation with the value on the internal binary counter during the execution of the self-refresh operation. When the value of the internal binary counter during the execution of the self-refresh operation coincides with the value at the start of the self-refresh operation, the counter comparator delivers a predetermined potential to an external I/O terminal, showing that the intensive refresh operation is not required.
A semiconductor memory circuit described in JP-P2001-283586A achieves a sufficient level of restore even when it uses a self-refresh operation which requires low current consumption. A delay amount switching circuit block switches a delay amount of an RTO signal, which defines deactivation of word lines in a self-refresh operation, to delay the RTO signal. The delay amount switching circuit block includes a path selector circuit which selects a signal path B for a CBR refresh operation and a signal path A for a self-refresh operation. The RTO signal is delayed by a predetermined time through the signal path A in the self-refresh operation. As a result, a row address strobe signal {overscore (RAS)} remains active for a longer period to extend a word line selection period. In the CBR refresh operation, the signal path B is selected so that the RTO signal is not delayed. In this way, the waveform of signal {overscore (RAS)} is adjusted in accordance with the length of the refresh operation cycle to achieve an appropriate level of restore.